Field of the Invention
The present invention relates to a shift register and, more particularly, to a shift register capable of reducing a circuit area through simplification of a logic circuit configuration and to a display device using the same.
Discussion of the Related Art
Representative examples of a flat display device recently highlighted as a display device include a liquid crystal display (LCD) using liquid crystals, an organic light emitting diode (OLED) display using OLEDs, an electrophoretic display (EPD) using electrophoretic particles, and the like.
Such a flat display device includes a display panel for displaying an image through a pixel matrix including pixels each independently driven by thin film transistors (TFTs), a panel driver for driving the display panel, and a timing controller for controlling the panel driver. The panel driver includes a gate driver for driving gate lines of the display panel, and a data driver for driving data lines of the display panel.
In recent years, a gate-in-panel (GIP) structure, in which a gate driver is formed on a substrate, together with a TFT array of a pixel matrix, has been mainly used in order to achieve a reduction in manufacturing costs and a reduction in bezel width. Such a GIP type gate driver is being developed toward a reduction in circuit area in order to achieve a further reduction in bezel width.
The gate driver outputs scan pulses to drive respective gate lines, using a shift register. The shift register includes a plurality of stages for driving a plurality of gate lines, respectively. Each stage includes an output unit and a node controller. The output unit of each stage basically includes a pull-up TFT for outputting a certain clock to the corresponding gate line under control of a Q-node, and a pull-down TFT for outputting a gate-low voltage to the gate line under control of a QB-node. The node controller of each stage includes a plurality of TFTs for controlling charge and discharge of the Q-node and charge and discharge of the QB-node in a reverse manner. In particular, the number of TFTs to maintain the QB-node in a high-level state is relatively great.
Meanwhile, in the case of a shift register configured to enable a bi-scan for selective utilization of a forward scan and a backward scan, each stage thereof should include a greater number of TFTs.
For this reason, in shift registers according to the related art, it is difficult to achieve a reduction in circuit area due to the use of a great number of TFTs and, as such, there is a limitation in realizing a narrow bezel.